1. Field Of The Invention
The present invention relates to analog silicon structures for performing the long term learning function in neural networks. More particularly, the present invention relates to floating gate MOS structures for performing the long term learning function.
2. The Prior Art
The most common form of prior art long-term non-volatile storage devices use charge stored on a floating silicon gate, embedded in pure silicon dioxide. The charge on such a gate will stay fixed for periods of many years. Devices using charge stored on floating gates require that charge be injected when it is desired to "write" the signal, but not leak off when the value of the stored signal is "read".
The first method 3.2 injecting charge through the oxide onto the floating gate was to avalanche a junction formed at one edge of the floating gate. The avalanche process creates an electron population with a broad energy distribution. Some of these electrons have enough energy to surmount the approximately 3.2 eV barrier from the conduction band of the silicon substrate to the oxide conduction band, so they can penetrate the oxide and end up on the floating gate. The avalanche process requires very high voltages and simultaneously high current, and is therefore very inconvenient to use as a learning mechanism.
A second charge-injection mechanism that has been employed in floating-gate structures is electron tunneling. When a sufficiently high electric field is placed across the oxide, electrons will tunnel from the substrate to the floating gate, or from one gate level to another. The rate at which this process takes place is a function only of the electric field, and requires high voltages (but not high currents).
Tunneling from the active layers to a floating polysilicon gate requires special processing to produce very thin oxides of very controlled thickness. To avoid this difficulty, tunneling from one polysilicon layer to another can be used. The oxidation of polycrystalline silicon produces sharp points (asperities) of remaining silicon that act as field-emission tips and greatly reduce the voltage required for tunneling. Using this technique, tunneling is a useful injection mechanism for a learning network using the oxide thicknesses available in a standard double-poly process. In a typical application, the first layer of polysilicon (poly-1) is used as the floating gate, and a small overlying patch of second layer polysilicon (poly-2) functions as the charge-injecting electrode.
The enhanced-tunneling mechanism is, by its very nature, asymmetrical. The inter-poly oxide is grown by oxidizing poly-1, and poly-2 is then deposited over the rather smooth oxide surface. There are no asperites on the bottom of poly-2 to enhance the electric field. For this reason, electrons can be removed from the floating poly-1 electrode by making the poly-2 plate positive, but a much higher voltage is required to inject electrons onto the poly-1. For a long term learning system, it is necessary to change the charge on the floating gate in either direction, i.e., to selectively remove electrons from, or add electrons to, the floating gate. Inter-poly tunneling can be conveniently used only to remove electrons from the floating gate. To add electrons to the floating gate would require another poly layer below the floating gate, and at a high negative voltage with respect to it. There is therefore an urgent need for a low-power, controllable mechanism by which electrons can be injected onto the floating gate without paying the high cost of a high voltage of the opposite sign of that required for electron removal.
One way to inject charge in a controllable way over many orders of magnitude in rate is to use a split-gate structure such as that described in U.S. Pat. No. 4,622,656. The split-gate structure is formed in a two-gate-level process, such as a standard double-polysilicon gate process commonly available commercially.
This split-gate injection mechanism requires high voltage on the floating gate of the split gate structure. This requirement causes great problems in the circuit design of sensing circuits attached thereto. For that reason, it is desirable to use an injection scheme in which the floating gate can be used at a potential within the power supply rails, and the voltage required for injection be supplied by an electrode other than the floating gate.
There is an urgent need of an analog silicon device structure for performing the long-term learning function in a neural network. Preferably such a device structure would use a standard, widely available, highly developed silicon process. Such a learning structure should be compatible with standard silicon processing. It should have a writing rate which is a non-linear function of both input and output signals (Delta Rule) and which is accurately controllable to very small values. In addition, such a structure should operate using writing currents and voltages within operating limits of standard devices on the same chip.